The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits.
A variety of techniques are used to stack integrated circuits. Some require that the circuits be encapsulated in special packages, while others use circuits in conventional packages. In some cases, the leads alone of packaged circuits have been used to create the stack and interconnect its constituent elements. In other techniques, structural elements such as rails are used to create the stack and interconnect the constituent elements.
Circuit boards in vertical orientations have been used to provide interconnection between stack elements. For example, in U.S. Pat. No. 5,514,907 to Moshayedi, a technique is described for creating a multi-chip module from surface-mount packaged memory chips. The devices are interconnected on their lead emergent edges through printed circuit boards oriented vertically to a carrier or motherboard that is contacted by connective sites along the bottom of the edge-placed PCBs. Japanese Patent Laid-open Publication No. Hei 6-77644 discloses vertical PCBs used as side boards to interconnect packaged circuit members of the stack.
Others have stacked integrated circuits without casings or carrier plates. Electrical conductors are provided at the edges of the semiconductor bodies and extended perpendicularly to the planes of the circuit bodies. Such a system is shown in U.S. Pat. No. 3,746,934 to Stein.
Still others have stacked packaged circuits using interconnection packages similar to the packages within which the integrated circuits of the stack are contained to route functionally similar terminal leads in non-corresponding lead positions. An example is found in U.S. Pat. No. 4,398,235 to Lutz et al. Simple piggyback stacking of DIPs has been shown in U.S. Pat. No. 4,521,828 to Fanning.
Some more recent methods have employed rail-like structures used to provide interconnection and structural integrity to the aggregated stack. The rails are either discrete elements that are added to the structure or are crafted from specific orientations of the leads of the constituent circuit packages. For example, in U.S. Pat. No. 5,266,834 to Nishi et al., one depicted embodiment illustrates a stack created by selective orientation of the leads of particularly configured stack elements, while in U.S. Pat. No. 5,343,075 to Nishino, a stack of semiconductor devices is created with contact plates having connective lines on inner surfaces to connect the elements of the stack.
More recently, sophisticated techniques have been developed for stacking integrated circuits. The assignee of the present invention has developed a variety of such techniques for stacking integrated circuits. In one such method, multiple conventional ICs are stacked and external leads are interconnected with one another by means of a rail assembly. The rails are made of flat strips of metal and the rails define apertures that receive the leads of the discrete IC packages. An example of this system is shown in U.S. Pat. No. 5,778,522 assigned to the assignee of the present invention.
An even more recent technique developed by the assignee of the present invention interconnects conventionally packaged ICs with flexible circuits disposed between stack elements. The flexible circuits include an array of flexible conductors supported by insulating sheets. Terminal portions of the flexible conductors are bent and positioned to interconnect appropriate leads of respective upper and lower IC packages.
Some of the previously described systems have required encapsulation of the constituent ICs in special packages. Still others have added rails that must be custom-fabricated for the application. Many have relied upon connections that substantially coincide with the vertical orientation of the stack and thus require more materials while often adding excessive height to the stack. Others that use PCBs have inhibited heat dissipation of the stack. Most have deficiencies that add expense or complexity or thermal inefficiency to stacked integrated circuits. What is needed therefore, is a technique and system for stacking integrated circuits that provides a thermally efficient, robust structure while not adding excessive height to the stack yet allowing production at reasonable cost with easily understood and managed materials.
The present invention provides a system and method for selectively stacking and interconnecting individual integrated circuit devices to create a high density integrated circuit module. It is principally designed for use with memory circuits, but can be employed to advantage with any integrated circuits where size conservation and use of duplicative circuitry are present considerations.
In a preferred embodiment, conventional TSOP memory circuits are vertically stacked one above the other. The stack consists of two packaged integrated circuits, but alternatives may employ greater numbers of ICs.
Connections between stack elements are made through carrier structures that provide inter-element connections that transit from one IC to another IC to conserve material and create a stack having improved air flow and consequent heat transference. This is accomplished by having the interelement connections substantially follow an axis that is substantially perpendicular to the vertical axis of the stack. The carrier structure and inter-element connections cooperate to adapt the inherent structural features of the leads of the constituent elements into a stack framework having appropriate integrity.
In a preferred embodiment, electronic connections between stack elements are supported by printed circuit board or other support material. The connection between elements is made by conductive paths disposed to provide connection between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element. This leaves open to air flow, most of the transit section of the lower lead for cooling, while creating an air gap between elements that encourages cooling airflow between the elements of the stack and minimizes fabrication complexity.
A method for creating stacked integrated circuit modules is provided that provides reasonable cost, mass production techniques to produce modules.